The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
The decreased geometry sizes lead to challenges in semiconductor manufacturing. For example, an organic layer used as an under layer in a lithography process may have compositions (e.g., monomers or polymers) dissolved in solvents from another layer coated above it (e.g., a middle layer or a photoresist layer), resulting in intermixed boundaries between different material layers. As geometry sizes continue to decrease, fabrication process tolerances are reduced, and the impact from intermixed boundaries will limit process windows such as exposing or etching process windows and further limit the critical dimension of a resist pattern formed in the lithography process.
Therefore, while traditional lithography process methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect. It is desired to have a lithography method to address the above issues.